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december 1995 order number: 290478-004 82433lx/82433nx local bus accelerator (lbx) y supports the full 64-bit pentium processor data bus at frequencies up to 66 mhz (82433lx and 82433nx) y drives 3.3v signal levels on the cpu data and address buses (82433nx) y provides a 64-bit interface to dram and a 32-bit interface to pci y five integrated write posting and read prefetch buffers increase cpu and pci performance e cpu-to-memory posted write buffer 4 qwords deep e pci-to-memory posted write buffer two buffers, 4 dwords each e pci-to-memory read prefetch buffer 4 qwords deep e cpu-to-pci posted write buffer 4 dwords deep e cpu-to-pci read prefetch buffer 4 dwords deep y cpu-to-memory and cpu-to-pci write posting buffers accelerate write performance y dual-port architecture allows concurrent operations on the host and pci buses y operates synchronously to the cpu and pci clocks y supports burst read and writes of memory from the host and pci buses y sequential cpu writes to pci converted to zero wait-state pci bursts with optional trdy y connection y byte parity support for the host and memory buses e optional parity generation for host to memory transfers e optional parity checking for the secondary cache e parity checking for host and pci memory reads e parity generation for pci to memory writes y 160-pin qfp package two 82433lx or 82433nx local bus accelerator (lbx) components provide a 64-bit data path between the host cpu/cache and main memory, a 32-bit data path between the host cpu bus and pci local bus, and a 32-bit data path between the pci local bus and main memory. the dual-port architecture allows concurrent operations on the host and pci buses. the lbxs incorporate three write posting buffers and two read prefetch buffers to increase cpu and pci performance. the lbx supports byte parity for the host and main memory buses. the 82433nx is intended to be used with the 82434nx pci/cache/memory controller (pcmc). the 82433lx is intended to be used with the 82434lx pcmc. during bus operations between the host, main memory and pci, the pcmc commands the lbxs to perform functions such as latching address and data, merging data, and enabling output buffers. together, these three components form a ``host bridge'' that provides a full function dual-port data path interface, linking the host cpu and pci bus to main memory. this document describes both the 82433lx and 82433nx. shaded areas, like this one, describe the 82433nx operations that differ from the 82433lx.
82433lx/82433nx 290478 1 lbx simplified block diagram 2
82433lx/82433nx local bus accelerator (lbx) contents page 1.0 architectural overview 5 1.1 buffers in the lbx 5 1.2 control interface groups 7 1.3 system bus interconnect 7 1.4 pci trdy y interface 8 1.5 parity support 8 2.0 signal descriptions 8 2.1 host interface signals 9 2.2 main memory (dram) interface signals 10 2.3 pci interface signals 10 2.4 pcmc interface signals 10 2.5 reset and clock signals 11 3.0 functional description 12 3.1 lbx post and prefetch buffers 12 3.1.1 cpu-to-memory posted write buffer 12 3.1.2 pci-to-memory posted write buffer 12 3.1.3 pci-to-memory read prefetch buffer 12 3.1.4 cpu-to-pci posted write buffer 13 3.1.5 cpu-to-pci read prefetch buffer 14 3.2 lbx interface command descriptions 14 3.2.1 host interface group: hig [ 4:0 ] 14 3.2.2 memory interface group: mig [ 2:0 ] 18 3.2.3 pci interface group: pig [ 3:0 ] 19 3.3 lbx timing diagrams 21 3.3.1 hig [ 4:0 ] command timing 21 3.3.2 hig [ 4:0 ] memory read timing 22 3.3.3 mig [ 2:0 ] command 23 3.3.4 pig [ 3:0 ] command, drvpci, and ppout timing 24 3.3.5 pig [ 3:0 ] : read prefetch buffer command timing 25 3.3.6 pig [ 3:0 ] : end-of-line warning signal: eol 27 3.4 pll loop filter components 29 3.5 pci clock considerations 30 3
contents page 4.0 electrical characteristics 31 4.1 absolute maximum ratings 31 4.2 thermal characteristics 31 4.3 dc characteristics 32 4.3.1 82433lx lbx dc characteristics 32 4.3.2 82433nx lbx dc characteristics 33 4.4 82433lx ac characteristics 35 4.4.1 host and pci clock timing, 66 mhz (82433lx) 35 4.4.2 command timing, 66 mhz (82433lx) 36 4.4.3 address, data, trdy y , eol, test, tscon and parity timing, 66 mhz (82433lx) 37 4.4.4 host and pci clock timing, 60 mhz (82433lx) 38 4.4.5 command timing, 60 mhz (82433lx) 38 4.4.6 address, data, trdy y , eol, test, tscon and parity timing, 60 mhz (82433lx) 39 4.4.7 test timing (82433lx) 40 4.5 82433nx ac characteristics 40 4.5.1 host and pci clock timing (82433nx) 40 4.5.2 command timing (82433nx) 41 4.5.3 address, data, trdy y , eol, test, tscon and parity timing (82433nx) 41 4.5.4 test timing (82433nx) 42 4.5.5 timing diagrams 43 5.0 pinout and package information 45 5.1 pin assignment 45 5.2 package information 50 6.0 testability 51 6.1 nand tree 51 6.1.1 test vector table 51 6.1.2 nand tree table 51 6.2 pll test mode 53 4
82433lx/82433nx 1.0 architectural overview the 82430 pciset consists of the 82434lx pcmc and 82433lx lbx components plus either a pci/ isa bridge or a pci/eisa bridge. the 82430nx pci- set consists of the 82434nx pcmc and 82433nx lbx components plus either a pci/isa bridge or a pci/eisa bridge. the pcmc and lbx provide the core cache and main memory architecture and serves as the host/pci bridge. an overview of the pcmc follows the system overview section. the local bus accelerator (lbx) provides a high performance data and address path for the 82430lx/82430nx pciset. the lbx incorporates five integrated buffers to increase the performance of the pentium processor and pci master devices. two lbxs in the system support the following areas: 1. 64-bit data and 32-bit address bus of the pentium processor. 2. 32-bit multiplexed address/data bus of pci. 3. 64-bit data bus of the main memory. in addition, the lbxs provide parity support for the three areas noted above (discussed further in sec- tion 1.4). 1.1 buffers in the lbx the lbx components have five integrated buffers designed to increase the performance of the host and pci interfaces of the 82430lx/82430nx pciset. with the exception of the pci-to-memory write buffer and the cpu-to-pci write buffer, the buffers in the lbx store data only, addresses are stored in the pcmc component. 5
82433lx/82433nx 290478 2 notes: 1. cpu-to-memory posted write buffer: this buffer is 4 qwords deep, enabling the pentium processor to write back a whole cache line in 4-1-1-1 timing, a total of 7 cpu clocks. 2. pci-to-memory posted write buffer: a pci master can post two consecutive sets of 4 dwords (total of one cache line) or two single non-consecutive transactions. 3. pci-to-memory read prefetch buffer: a pci master to memory read transaction will cause this prefetch buffer to read up to 4 qwords of data from memory, allowing up to 8 dwords to be read onto pci in a single burst transaction. 4. cpu-to-pci posted write buffer: the pentium processor can post up to 4 dwords into this buffer. the trdy y connect option allows zero-wait state burst writes to pci, making this buffer especially useful for graphic write operations. 5. cpu-to-pci read prefetch buffer: this prefetch buffer is 4 dwords deep, enabling faster sequential pentium proc- essor reads when targeting pci. figure 1. simplified block diagram of the lbx data buffers 6
82433lx/82433nx 1.2 control interface groups the lbx is controlled by the pcmc via the control interface group signals. there are three interface groups: host, memory, and pci. these control groups are signal lines that carry binary codes which the lbx internally decodes in order to implement specific functions such as latching data and steering data from pci to memory. the control interfaces are described below. 1. host interface group: these control signals are named hig [ 4:0 ] and define a total of 29 (30 for the 82433nx) discrete commands. the pcmc sends hig commands to direct the lbx to per- form functions related to buffering and storing host data and/or address. 2. memory interface group: these control signals are named mig [ 2:0 ] and define a total of 7 dis- crete commands. the pcmc sends mig com- mands to direct the lbx to perform functions re- lated to buffering, storing, and retiring data to memory. 3. pci interface group: these control signals are named pig [ 3:0 ] and define a total of 15 discrete commands. the pcmc sends pig commands to direct the lbx to perform functions related to buffering and storing pci data and/or address. 1.3 system bus interconnect the architecture of the 82430/82430nx pciset splits the 64-bit memory and host data buses into logical halves in order to manufacture lbx devices with manageable pin counts. the two lbxs interface to the 32-bit pci ad [ 31:0 ] bus with 16 bits each. each lbx connects to 16 bits of the ad [ 31:0 ] bus and 32-bits of both the md [ 0:63 ] bus and the d [ 0:63 ] bus. the lower order lbx (lbxl) connects to the low word of the ad [ 31:0 ] bus, while the high order lbx (lbxh) connects to the high word of the ad [ 31:0 ] bus. since the pci connection for each lbx falls on 16-bit boundaries, each lbx does not simply con- nect to either the low dword or high dword of the qword memory and host buses. instead, the low or- der lbx buffers the first and third words of each 64-bit bus while the high order lbx buffers the sec- ond and fourth words of the memory and host buses. as shown in figure 2, lbxl connects to the first and third words of the 64-bit main memory and host data buses. the same device also drives the first 16 bits of the host address bus, a [ 15:0 ] . the lbxh device connects to the second and fourth words of the 64-bit main memory and host data buses. corre- spondingly, lbxh drives the remaining 16 bits of the host address bus, a [ 31:16 ] . 290478 3 figure 2. simplified interconnect diagram of lbxs to system buses 7
82433lx/82433nx 1.4 pci trdy y interface the pci control signals do not interface to the lbxs, instead these signals connect to the 82434lx pcmc component. the main function of the lbxs pci interface is to drive address and data onto pci when the cpu targets pci and to latch address and data when a pci master targets main memory. the trdy y option provides the capability for zero- wait state performance on pci when the pentium processor performs sequential writes to pci. this option requires that pci trdy y be connected to each lbx, for a total of two additional connections in the system. these two trdy y connections are in addition to the single trdy y connection that the pcmc requires. 1.5 parity support the lbxs support byte parity on the host bus (cpu and second level cache) and main memory buses (local dram). the lbxs support parity during the address and data phases of pci transactions to/ from the host bridge. 2.0 signal descriptions this section provides a detailed description of each signal. the signals (figure 3) are arranged in func- tional groups according to their associated interface. the ` y ' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ` y ' is not pres- ent after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used exten- sively. this is done to avoid confusion when working with a mixture of `active-low' and `active-high' sig- nals. the term assert ,or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term ne- gate ,or negation indicates that a signal is inactive. the following notations are used to describe the sig- nal type. in input is a standard input-only signal. out totem pole output is a standard active driver. t/s tri-state is a bi-directional, tri-state input/out- put pin. 290478 4 figure 3. lbx signals 8
82433lx/82433nx 2.1 host interface signals signal type description a [ 15:0 ] t/s address bus: the bi-directional a [ 15:0 ] lines are connected to the address lines of the host bus. the high order lbx (determined at reset time using the eol signal) is connected to a [ 31:16 ] , and the low order lbx is connected to a [ 15:0 ] . the host address bus is common with the pentium processor, second level cache, pcmc and the two lbxs. during cpu cycles a [ 31:3 ] are driven by the cpu and a [ 2:0 ] are driven by the pcmc, all are inputs to the lbxs. during inquire cycles the lbx drives the pci master address onto the host address lines a [ 31:0 ] . this snoop address is driven to the cpu and the pcmc by the lbxs to snoop l1 and the integrated second level tags, respectively. during pci configuration cycles bound for the pcmc, the lbxs will send or receive the configuration data to/from the pcmc by copying the host data bus to/from the host address bus. the lbx drives both halves of the qword host data bus with data from the 32-bit address during pcmc configuration read cycles. the lbx drives the 32-bit address with either the low dword or the high dword during pcmc configuration write cycles. in the 82433nx, these pins contain weak internal pull-down resistors. the high order 82433nx lbx samples a11 at the falling edge of reset to configure the lbx for pll test mode. when a11 is sampled low, the lbx is in normal operating mode. when a11 is sampled high, the lbx drives the internal hclk from the pll on the eol pin. note that a11 on the high order lbx is connected to the a27 line on the cpu address bus. this same address line is used to put the pcmc into pll test mode. d [ 31:0 ] t/s host data: the bi-directional d [ 31:0 ] lines are connected to the data lines of the host data bus. the high order lbx (determined at reset time using the eol signal) is connected to the host data bus d [ 63:48 ] and d [ 31:16 ] lines, and the low order lbx is connected to the host data bus d [ 47:32 ] and d [ 15:0 ] lines. in the 82433lx, these pins contain weak internal pull-up resistors. in the 82433nx, these pins contain weak internal pull-down resistors. hp [ 3:0 ] t/s host data parity: hp [ 3:0 ] are the bi-directional byte parity signals for the host data bus. the low order parity bit hp [ 0 ] corresponds to d [ 7:0 ] while the high order parity bit hp [ 3 ] corresponds to d [ 31:24 ] . the hp [ 3:0 ] signals function as parity inputs during write cycles and as parity outputs during read cycles. even parity is supported and the hp [ 3:0 ] signals follow the same timings as d [ 31:0 ] . in the 82433lx, these pins contain weak internal pull-up resistors. in the 82433nx, these pins contain weak internal pull-down resistors. 9
82433lx/82433nx 2.2 main memory (dram) interface signals signal type description md [ 31:0 ] t/s memory data bus: md [ 31:0 ] are the bi-directional data lines for the memory data bus. the high order lbx (determined at reset time using the eol signal) is connected to the memory data bus md [ 63:48 ] and md [ 31:16 ] lines, and the low order lbx is connected to the memory data bus md [ 47:32 ] and md [ 15:0 ] lines. the md [ 31:0 ] signals drive data destined for either the host data bus or the pci bus. the md [ 31:0 ] signals input data that originated from either the host data bus or the pci bus. these pins contain weak internal pull-up resistors. mp [ 3:0 ] t/s memory parity: mp [ 3:0 ] are the bi-directional byte enable parity signals for the memory data bus. the low order parity bit mp [ 0 ] corresponds to md [ 7:0 ] while the high order parity bit mp [ 3 ] corresponds to md [ 31:24 ] . the mp [ 3:0 ] signals are parity outputs during write cycles to memory and parity inputs during read cycles from memory. even parity is supported and the mp [ 3:0 ] signals follow the same timings as md [ 31:0 ] . these pins contain weak internal pull-up resistors. 2.3 pci interface signals signal type description ad [ 15:0 ] t/s address and data: ad [ 15:0 ] are bi-directional data lines for the pci bus. the ad [ 15:0 ] signals sample or drive the address and data on the pci bus. the high order lbx (determined at reset time using the eol signal) is connected to the pci bus ad [ 31:16 ] lines, and the low order lbx is connected to the pci ad [ 15:0 ] lines. trdy y in target ready: trdy y indicates the selected (targeted) device's ability to complete the current data phase of the bus operation. for normal operation, trdy y is tied asserted low. when the trdy y option is enabled in the pcmc (for zero wait-state pci burst writes), trdy y should be connected to the pci bus. 2.4 pcmc interface signals signal type description hig [ 4:0 ] in host interface group: these signals are driven from the pcmc and control the host interface of the lbx. the 82433lx decodes the binary pattern of these lines to perform 29 unique functions (30 for the 83433nx). these signals are synchronous to the rising edge of hclk. mig [ 2:0 ] in memory interface group: these signals are driven from the pcmc and control the memory interface of the lbx. the lbx decodes the binary pattern of these lines to perform 7 unique functions. these signals are synchronous to the rising edge of hclk. pig [ 3:0 ] in pci interface group: these signals are driven from the pcmc and control the pci interface of the lbx. the lbx decodes the binary pattern of these lines to perform 15 unique functions. these signals are synchronous to the rising edge of hclk. mdle in memory data latch enable: during cpu reads from dram, the lbx uses a clocked register to transfer data from the md [ 31:0 ] and mp [ 3:0 ] lines to the d [ 31:0 ] and hp [ 3:0 ] lines. mdle is the clock enable for this register. data is clocked into this register when mdle is asserted. the register retains its current value when mdle is negated. during cpu reads from main memory, the lbx tri-states the d [ 31:0 ] and hp [ 3:0 ] lines on the rising edge of mdle when hig [ 4:0 ] e nopc. drvpci in drive pci bus: this signals enables the lbx to drive either address or data information onto the pci ad [ 15:0 ] lines. 10
82433lx/82433nx 2.4 pcmc interface signals (continued) signal type description eol t/s end of line: this signal is asserted when a pci master read or write transaction is about to overrun a cache line boundary. the low order lbx will have this pin connected to the pcmc (internally pulled up in the pcmc). the high order lbx connects this pin to a pull- down resistor. with one lbx eol line being pulled down and the other lbx eol pulled up, the lbx samples the value of this pin on the negation of the reset signal to determine if it's the high or low order lbx. ppout t/s lbx parity: this signal reflects the parity of the 16 ad lines driven from or latched into the lbx, depending on the command driven on pig [ 3:0 ] . the pcmc uses ppout from both lbxs (called ppout [ 1:0 ] ) to calculate the pci parity signal (par) for cpu to pci transactions during the address phase of the pci cycle. the lbx uses ppout to check the par signal for pci master transactions to memory during the address phase of the pci cycle. when transmitting data to pci the pcmc uses ppout to calculate the proper value for par. when receiving data from pci the pcmc uses ppout to check the value received on par. if the l2 cache does not implement parity, the lbx will calculate parity so the pcmc can drive the correct value on par during l2 reads initiated by a pci master. the lbx samples the ppout signal at the negation of reset and compares that state with the state of eol to determine whether the l2 cache implements parity. the pcmc internally pulls down ppout [ 0 ] and internally pulls up ppout [ 1 ] . the l2 supports parity if ppout [ 0 ] is connected to the high order lbx and ppout [ 1 ] is connected to the low order lbx. the l2 is defined to not support parity if these connections are reversed, and for this case, the lbx will calculate parity. for normal operations either connection allows proper parity to be driven to the pcmc. 2.5 reset and clock signals signal type description hclk in host clock: hclk is input to the lbx to synchronize command and data from the host and memory interfaces. this input is derived from a buffered copy of the pcmc hclkx output. pclk in pci clock: all timing on the lbx pci interface is referenced to the pclk input. all output signals on the pci interface are driven from pclk rising edges and all input signals on the pci interface are sampled on pclk rising edges. this input is derived from a buffered copy of the pcmc pclk output. reset in reset: assertion of this signal resets the lbx. after reset has been negated the lbx configures itself by sampling the eol and ppout pins. reset is driven by the pcmc cpurst pin. the reset signal is synchronous to hclk and must be driven directly by the pcmc. lp1 out loop 1: phase lock loop filter pin. the filter components required for the lbx are connected to these pins. lp2 in loop 2: phase lock loop filter pin. the filter components required for the lbx are connected to these pins. test in test: the test pin must be tied low for normal system operation. tscon in tri-state control: this signal enables the output buffers on the lbx. this pin must be held high for normal operation. if tscon is negated, all lbx outputs will tri-state. 11
82433lx/82433nx 3.0 functional description 3.1 lbx post and prefetch buffers this section describes the five write posting and read prefetching buffers implemented in the lbx. the discussion in this section refers to the operation of both lbxs in the system. 3.1.1 cpu-to-memory posted write buffer the write buffer is a queue 4 qwords deep, it loads qwords from the cpu and stores qwords to memo- ry. it is 4 qwords deep to accommodate write-backs from the first or second level cache. it is organized as a simple fifo. commands driven on the hig [ 4:0 ] lines store qwords into the buffer, while commands on the mig [ 2:0 ] lines retire qwords from the buffer. while retiring qwords to memory, the dram control- ler unit of the pcmc will assert the appropriate ma, cas [ 7:0 ] y , and we y signals. the pcmc keeps track of full/empty states, status of the data and address. byte parity for data to be written to memory is either propagated from the host bus or generated by the lbx. the lbx generates parity for data from the second level cache when the second level cache does not implement parity. 3.1.2 pci-to-memory posted write buffer the buffer is organized as 2 buffers (4 dwords each). there is an address storage register for each buffer. when an address is stored one of the two buffers is allocated and subsequent dwords of data are stored beginning at the first location in that buff- er. buffers are retired to memory strictly in order, qword at a time. commands driven on the pig [ 3:0 ] lines post ad- dresses and data into the buffer. commands driven on hig [ 4:0 ] result in addresses being driven on the host address bus. commands driven on mig [ 2:0 ] result in data being retired to dram. for cases where the address targeted by the first dword is odd, i.e. a [ 2 ] e 1, and the data is stored in an even location in the buffer, the lbx correctly aligns the dword when retiring the data to dram. in other words the buffer is capable of retiring a qword to memory where the data in the buffer is shifted by 1 dword (dword is position 0 shifted to 1, 1 shifted to 2 etc.). the dram controller of the pcmc asserts the correct cas [ 7:0 ] y signals depending on the pci c/be [ 3:0 ] y signals stored in the pcmc for that dword. the end of line (eol) signal is used to prevent pci master writes from bursting past the cache line boundary. the device that provides ``warning'' to the pcmc is the low order lbx. this device contains the pci master write low order address bits necessary to determine how many dwords are left to the end of the line. consequently, the lbx protocol uses the eol signal from the low order lbx to provide this ``end-of-line'' warning to the pcmc, so that it may retry a pci master write when it bursts past the cache line boundary. this protocol is described fully in section 3.3.6. the lbx calculates dword parity on pci write data, sending the proper value to the pcmc on ppout. the lbx generates byte parity on the mp signals for writing into dram. 3.1.3 pci-to-memory read prefetch buffer this buffer is organized as a line buffer (4 qwords) for burst transfers to pci. the data is transferred into the buffer a qword at a time and read out a dword at a time. the lbx then effectively decouples the memory read rate from the pci rate to increase con- currence. each new transaction begins by storing the first dword in the first location in the buffer. the starting dword for reading data out of the buffer onto pci must be specified within a qword boundary; that is the first requested dword on pci could be an even or odd dword. if the snoop for a pci master read results in a write-back from first or second level caches, this write back is sent directly to pci and main memory. the following two paragraphs de- scribe this process for cache line write-backs. since the write-back data from l1 is in linear order, writing into the buffer is straightforward. only those qwords to be transferred into pci are latched into the pci-to-memory read buffer. for example, if the address targeted by pci is in the 3rd or 4th qword in the line, the first 2 qwords of write back data are discarded and not written into the read buffer. the primary cache write-back must always be written 12
82433lx/82433nx completely to the cpu-to-memory posted write buffer. if the pci master read data is read from the second- ary cache, it is not written back to memory. write- backs from the second level cache, when using burst srams, are in pentium processor burst order (the order depending on which qword of the line is targeted by the pci read). the buffer is directly ad- dressed when latching second level cache write- back data to accommodate this burst order. for ex- ample, if the requested qword is qword 1, then the burst order is 1-0-3-2. qword 1 is latched in buffer location 0, qword 0 is discarded, qword 3 is latched into buffer location 2 and qword 2 is latched into buffer location 1. commands driven on mig [ 2:0 ] and hig [ 4:0 ] enter data into the buffer from the dram interface and the host interface (i.e. the caches), respectively. com- mands driven on the pig [ 3:0 ] lines drive data from the buffer onto the pci ad [ 31:0 ] lines. parity driven on the ppout signal is calculated from the byte parity received on the host bus or the mem- ory bus, whichever is the source. if the second level cache is the source of the data and does not imple- ment parity, the parity driven on ppout is generated by the lbx from the second level cache data. if main memory is the source of the read data, pci parity is calculated from the dram byte parity. main memory must implement byte parity to guarantee correct pci parity generation. 3.1.4 cpu-to-pci posted write buffer the cpu-to-pci posted write buffer is 4 dwords deep. the buffer is constructed as a simple fifo, with some performance enhancements. an address is stored in the lbx with each dword of data. the structure of the buffer accommodates the packetiza- tion of writes to be burst on pci. this is accom- plished by effectively discarding addresses of data dwords driven within a burst. thus, while an address is stored for each dword, an address is not neces- sarily driven on pci for each dword. the pcmc de- termines when a burst write may be performed based on consecutive addresses. the buffer also enables consecutive bytes to be merged within a single dword, accommodating byte, word, and misa- ligned dword string store and string move opera- tions. qword writes on the host bus are stored within the buffer as two individual dword writes, with sepa- rate addresses. the storing of an address with each dword of data allows burst writes to be retried easily. in order to retry transactions, the fifo is effectively ``backed up'' by one dword. this is accomplished by making the fifo physically one entry larger than it is logical- ly. thus, the buffer is physically 5 entries deep (an entry consists of an address and a dword of data), while logically it is considered full when 4 entries have been posted. this design allows the fifo to be backed up one entry when it is logically full. commands driven on hig [ 4:0 ] post addresses and data into the buffer, and commands driven on pig [ 3:0 ] retire addresses and data from the buffer and drive them onto the pci ad [ 31:0 ] lines. as dis- cussed previously, when bursting, not all addresses are driven onto pci. data parity driven on the ppout signal is calculated from the byte parity received on the host bus. ad- dress parity driven on ppout is calculated from the address received on the host bus. 13
82433lx/82433nx 3.1.5 cpu-to-pci read prefetch buffer this prefetch buffer is organized as a single buffer 4 dwords deep. the buffer is organized as a simple fifo. reads from the buffer are sequential; the buff- er does not support random access of its contents. to support reads of less than a dword the fifo read pointer can function with or without a pre-incre- ment. the pointer can also be reset to the first entry before a dword is driven. when a dword is read, it is driven onto both halves of the host data bus. commands driven on the hig [ 4:0 ] lines enable read addresses to be sent onto pci, the addresses are driven using pig [ 3:0 ] commands. read data is latched into the lbx by commands driven on the pig [ 3:0 ] lines and the data is driven onto the host data bus using commands driven on the hig [ 4:0 ] lines. the lbx calculates dword parity on pci read data, sending the proper value to the pcmc on ppout. the lbx does not generate byte parity on the host data bus when the cpu reads pci. 3.2 lbx interface command descriptions this section describes the functionality of the hig, mig and pig commands driven by the pcmc to the lbxs. 3.2.1 host interface group: hig [ 4:0 ] the host interface commands are shown in table 1. these commands are issued by the host interface of the pcmc to the lbxs in order to perform the fol- lowing functions: # reads from cpu-to-pci read prefetch buffer when the cpu reads from pci. # stores write-back data to pci-to-memory read prefetch buffer when pci read address results in a hit to a modified line in first or second level caches. # posts data to cpu-to-memory write buffer in the case of a cpu to memory write. # posts data to cpu-to-pci write buffer in the case of a cpu to pci write. # drives host address to data lines and data to ad- dress lines for programming the pcmc configura- tion registers. 14
82433lx/82433nx table 1. hig commands command code description nopc 00000b no operation on cpu bus cmr 11100b cpu memory read cprf 00100b cpu read first dword from cpu-to-pci read prefetch buffer cpra 00101b cpu read next dword from cpu-to-pci read prefetch buffer, toggle a cprb 00110b cpu read next dword from cpu-to-pci read prefetch buffer, toggle b cprq 00111b cpu read qword from cpu-to-pci read prefetch buffer swb0 01000b store write-back data qword 0 to pci-to-memory read buffer swb1 01001b store write-back data qword 1 to pci-to-memory read buffer swb2 01010b store write-back data qword 2 to pci-to-memory read buffer swb3 01011b store write-back data qword 3 to pci-to-memory read buffer pcmwq 01100b post to cpu-to-memory write buffer qword pcmwfq 01101b post to cpu-to-memory write and pci-to-memory read buffer first qword pcmwnq 01110b post to cpu-to-memory write and pci-to-memory read buffer next qword pcpwl 10000b post to cpu-to-pci write low dword mcp3l 10011b merge to cpu-to-pci write low dword 3 bytes mcp2l 10010b merge to cpu-to-pci write low dword 2 bytes mcp1l 10001b merge to cpu-to-pci write low dword 1 byte pcpwh 10100b post to cpu-to-pci write high dword mcp3h 10111b merge to cpu-to-pci write high dword 3 bytes mcp2h 10110b merge to cpu-to-pci write high dword 2 bytes mcp1h 10101b merge to cpu-to-pci write high dword 1 byte lcprad 00001b latch cpu-to-pci read address dpra 11000b drive address from pci a/d latch to cpu address bus dpwa 11001b drive address from pci-to-memory write buffer to cpu address bus adcpy 11101b address to data copy in the lbx dacpyh 11011b data to address copy in the lbx high dword dacpyl 11010b data to address copy in the lbx low dword pscd 01111b post special cycle data drvff 11110b drive ff..ff (all 1's) onto the host data bus pcpwhc 00011b post to cpu-to-pci write high dword configuration note: all other patterns are reserved. 15
82433lx/82433nx nopc no operation is performed on the host bus by the lbx hence it tri-states its host bus drivers. cmr this command effectively drives dram data onto the host data bus. the lbx acts as a transparent latch in this mode, depending on mdle for latch control. with the mdle signal high the cmr command will cause the lbxs to buffer memory data onto the host bus. when mdle is low. the lbx will drive onto the host bus whatever memory data that was latched when mdle was negated. cprf this command reads the first dword of the cpu-to-pci read prefetch buffer. the read pointer of the fifo is set to point to the first dword. the dword is driven onto the high and low halves of the host data bus. cpra this command increments the read pointer of the cpu-to-pci read pre- fetch buffer fifo and drives that dword onto the host bus when it is driven after a cprf or cprb com- mand. if driven after another cpra command, the lbx drives the current dword while the read pointer of the fifo is not incremented. the dword is driven onto the upper and lower halves of the host data bus. cprb this command increments the read pointer of the cpu-to-pci read pre- fetch buffer fifo and drives that dword onto the host bus when it is driven after a cpra command. if driv- en after another cprb command, the lbx drives the current dword while the read pointer of the fifo is not incre- mented. the dword is driven onto the upper and lower halves of the host data bus. cprq this command drives the first dword stored in the cpu-to-pci read prefetch buffer onto the lower half of the host data bus, and drives the second dword onto the upper half of the host data bus, regardless of the state of the read pointer. the read pointer is not affect- ed by this command. swb0 this command stores a qword from the host data lines into location 0 of the pci-to-memory read buffer. parity is either generated for the data or prop- agated from the host bus based on the state of the ppout signals sampled at the negation of reset when the lbxs were initialized. swb1 this command, (similar to swb0), stores a qword from the host data lines into location 1 of the pci-to-mem- ory read buffer. parity is either gener- ated from the data or propagated from the host bus based on the state of the ppout signal sampled at the falling edge of reset. swb2 this command, (similar to swb0), stores a qword written back from the first or second level cache into location 2 of the pci-to-memory read buffer. parity is either generated from the data or propagated from the host bus based on the state of the ppout signal sam- pled at the falling edge of reset. swb3 this command stores a qword from the host data lines into location 3 of the pci-to-memory read buffer. parity is either generated for the data or prop- agated from the host bus based on the state of the ppout signal sampled at the falling edge of reset. pcmwq this command posts one qword of data from the host data lines to cpu- to-memory write buffer in case of a cpu memory write or a write-back from the second level cache. pcmwfq if the pci memory read address leads to a hit on a modified line in the first level cache, then a write-back is scheduled and this data has to be writ- ten into the cpu-to-memory write buff- er and pci-to-memory read buffer at the same time. the write-back of the first qword is done by this command to both the buffers. pcmwnq this command follows the previous command to store or post subsequent write-back qwords. 16
82433lx/82433nx pcpwl this command posts the low dword of a cpu-to-pci write. the cpu-to-pci write buffer stores a dword of pci ad- dress for every dword of data. hence, this command also stores the address of the low dword in the address loca- tion for the data. address bit 2 (a2) is not stored directly. this command as- sumes a value of 0 for a2 and this is what is stored. mcp3l this command merges the 3 most sig- nificant bytes of the low dword of the host data bus into the last dword post- ed to the cpu-to-pci write buffer. the address is not modified. mcp2l this command merges the 2 most sig- nificant bytes of the low dword of the host data bus into the last dword post- ed to the cpu-to-pci write buffer. the address is not modified. mcp1l this command merges the most signif- icant byte of the low dword of the host data bus into the last dword posted to the cpu-to-pci write buffer. the ad- dress is not modified. pcpwh this command posts the upper dword of a cpu-to-pci write, with its address, into the address location. hence, to do a qword write pcpwl has to be fol- lowed by a pcpwh. address bit 2 (a2) is not stored directly. this command forces a value of 1 for a2 and this is what is stored. mcp3h this command merges the 3 most sig- nificant bytes of the high dword of the host data bus into the last dword post- ed to the cpu-to-pci write buffer. the address is not modified. mcp2h this command merges the 2 most sig- nificant bytes of the high dword of the host data bus into the last dword post- ed to the cpu-to-pci write buffer. the address is not modified. mcp1h this command merges the most signif- icant byte of the high dword of the host data bus into the last dword posted to the cpu-to-pci write buffer. the ad- dress is not modified. lcprad this command latches the host ad- dress to drive on pci for a cpu-to-pci read. it is necessary to latch the ad- dress in order to drive inquire address- es on the host address bus before the cpu address is driven onto pci. dpra the pci memory read address is latched in the pci a/d latch by a pig command lcprad, this address is driven onto the host address bus by dpra. used in pci to memory read transaction. dpwa the dpwa command drives the ad- dress of the current pci master write buffer onto the host address bus. this command is potentially driven for multi- ple cycles. when it is no longer driven, the read pointer will increment to point to the next buffer, and a subsequent dpwa command will read the address from that buffer. adcpy this command drives the host data bus with the host address. the ad- dress is copied on the high and low halves of the qword data bus; i.e. a [ 31:0 ] is copied onto d [ 31:0 ] and d [ 63:32 ] . this command is used when the cpu writes to the pcmc configura- tion registers. dacpyh this command drives the host address bus with the high dword of host data. this command is used when the cpu writes to the pcmc configuration regis- ters. dacpyl this command drives the host address bus with the low dword of host data. this command is used when the cpu writes to the pcmc configuration regis- ters. pscd this command is used to post the val- ue of the special cycle code into the cpu-to-pci posted write buffer. the value is driven onto the a [ 31:0 ] lines by the pcmc, after acquiring the ad- dress bus by asserting ahold. the value on the a [ 31:0 ] lines is posted into the data location in the cpu-to- pci posted write buffer. drvff this command causes the lbx to drive all ``1s'' (i.e. ffffffffh) onto the host data bus. it is used for cpu reads from pci that terminate with master abort. pcpwhc this command posts the high half of the cpu data bus. the lbxs post the high half of the data bus even if a2 from the pcmc is low. this command is used during configuration writes when using pci configuration access mechanism y 1. 17
82433lx/82433nx 3.2.2 memory interface group: mig [ 2:0 ] the memory interface commands are shown in table 2. these commands are issued by the dram controller of the pcmc to perform the following functions: # retires data from cpu-to-memory write buffer to dram. # stores data into pci-to-memory read buffer when the pci read address is targeted to dram. # retires pci-to-memory write buffer to dram. table 2. mig commands command code description nopm 000b no operation on memory bus pmrfq 001b place into pci-to-memory read buffer first qword pmrnq 010b place into pci-to-memory read buffer next qword rcmwq 100b retire cpu-to-memory write buffer qword rpmwq 101b retire pci-to-memory write buffer qword rpmwqs 110b retire pci-to-memory write buffer qword shifted memdrv 111b drive latched data onto memory bus for 1 clock cycle note: all other patterns are reserved. nopmn operation on the memory bus. the lbx tri-states its drivers driving the memory bus. pmrfq the pci-to-memory read address tar- gets memory if there is a miss on first and second caches. this command stores the first qword of data starting at the first location in the buffer. this buff- er is 8 dwords or 1 cache line deep. pmrnq this command stores subsequent qwords from memory starting at the next available location in the pci-to- memory read buffer. it is always used after pmrfq. rcmwq this command retires one qword from the cpu-to-memory write buffer to dram. the address is stored in the ad- dress queue for this buffer in the pcmc. rpmwq this command retires one qword of data from one line of the pci-to-memo- ry write buffer to dram. when all the valid data in one buffer is retired, the next rpmwq (or rpmwqs) will read data from the next buffer. rpmwqs this command retires one qword of data from one line of pci-to-memory write buffer to dram. for this com- mand the data in the buffer is shifted by one dword (dword in position 0 is shift- ed to 1, 1 to 2 etc.). this is because the address targeted by the first dword of the write could be an odd dword (i.e., address bit [ 2 ] is a 1). to retire a misa- ligned line this command has to be used for all the data in the buffer. when all the valid data in one buffer is retired, the next rpmwq (or rpmwqs) will read data from the next buffer. memdrv for a memory write operation the data on the memory bus is required for more than one clock cycle hence all dram retires are latched and driven to the memory bus in subsequent cycles by this command. 18
82433lx/82433nx 3.2.3 pci interface group: pig [ 3:0 ] the pci interface commands are shown in table 3. these commands are issued by the pci master/ slave interface of the pcmc to perform the following functions: # slave posts address and data to pci-to-memory write buffer. # slave sends pci-to-memory read data on the ad bus. # slave latches pci master memory address so that it can be gated to the host address bus. # master latches cpu-to-pci read data from the ad bus. # master retires cpu-to-pci write buffer. # master sends cpu-to-pci address to the ad bus. the pci ad [ 31:0 ] lines are driven by asserting the signal drvpci. this signal is used for both master and slave transactions. parity is calculated on either the value being driven onto pci or the value being received on pci, de- pending on the command. in table 3, the par col- umn has been included to indicate the value that the ppout signals are based on. an ``i'' indicates that the ppout signals reflect the parity of the ad lines as inputs to the lbx. an ``o'' indicates that the ppout signals reflect the value being driven on the pci ad lines. see section 3.3.4 for the timing rela- tionship between the pig [ 3:0 ] command, the ad [ 31:0 ] lines, and the ppout signals. table 3. pig commands command code par description ppmwa 1000b i post to pci-to-memory write buffer address ppmwd 1001b i post to pci-to-memory write buffer data spmrh 1101b o send pci master read data high dword spmrl 1100b o send pci master read data low dword spmrn 1110b o send pci master read data next dword lcprf 0000b i latch cpu read from pci into read prefetch buffer first dword lcpra 0001b i latch cpu read from pci into prefetch buffer next dword, a toggle lcprb 0010b i latch cpu read from pci into prefetch buffer next dword, b toggle dcpwa 0100b o drive cpu-to-pci write buffer address dcpwd 0101b o drive cpu-to-pci write buffer data dcpwl 0110b o drive cpu-to-pci write buffer last data dccpd 1011b o discard current cpu-to-pci write buffer data bcpwr 1010b o backup cpu-to-pci write buffer for retry scpa 0111b o send cpu-to-pci address lpma 0011b i latch pci master address note: all other patterns are reserved. 19
82433lx/82433nx ppmwa this command selects a new buffer and places the pci master address latch value into the address register for that buffer. the next ppmwd command posts write data in the first location of this newly selected buff- er. this command also causes the eol logic to decrement the count of dwords remaining in the line. ppmwd this command stores the value in the ad latch into the next data loca- tion in the currently selected buffer. this command also causes the eol logic to decrement the count of dwords remaining in the line. spmrh this command sends the high order dword from the first qword of the pci-to-memory read buffer onto pci. this command also causes the eol logic to decrement the count of dwords remaining in the line. spmrl this command sends the low order dword from the first qword of the pci-to-memory read buffer onto pci. this command also selects the dword alignment for the transaction and causes the eol logic to decre- ment the count of dwords remaining in the line. spmrn this command sends the next dword from the pci-to-memory read buffer onto pci. this com- mand also causes the eol logic to decrement the count of dwords re- maining in the line. this command is used for the second and all subse- quent dwords of the current transac- tion. lcprf this command acquires the value of the ad [ 31:0 ] lines into the first loca- tion in the cpu-to-pci read pre- fetch buffer until a different com- mand is driven. lcpra when driven after a lcprf or lcprb command, this command latches the value of the ad [ 31:0 ] lines into the next location into the cpu-to-pci read prefetch buffer. when driven after another lcpra command, this command latches the value on ad [ 31:0 ] into the same location in the cpu-to-pci read prefetch buffer, overwriting the pre- vious value. lcprb when driven after a lcpra com- mand, this command latches the val- ue of the ad [ 31:0 ] lines into the next location into the cpu-to-pci read prefetch buffer. when driven after another lcprb command, this com- mand latches the value on ad [ 31:0 ] into the same location in the cpu-to- pci read prefetch buffer, overwrit- ing the previous value. dcpwa this command drives the next ad- dress in the cpu-to-pci write buffer onto pci. the read pointer of the fifo is not incremented. dcpwd this command drives the next data dword in the cpu-to-pci write buff- er onto pci. the read pointer of the fifo is incremented on the next pclk if trdy y is asserted. dcpwl this command drives the previous data dword in the cpu-to-pci write buffer onto pci. this is the data which was driven by the last dcpwd command. the read pointer of the fifo is not incremented. dccpd this command discards the current dword in the cpu-to-pci write buff- er. this is used to clear write data when the write transaction termi- nates with master abort, where trdy y is never asserted. bcpwr for this command the cpu-to-pci write buffer is ``backed up'' one en- try such that the address/data pair last driven with the dcpwa and dcpwd commands will be driven again on the ad [ 31:0 ] lines when the commands are driven again. this command is used when the tar- get has retried the write cycle. scpa this command drives the value on the host address bus onto pci. lpma this command stores the previous ad [ 31:0 ] value into the pci master address latch. if the eol logic deter- mines that the requested dword is the last dword of a line, then the eol signal will be asserted; other- wise the eol signal will be negated. 20
82433lx/82433nx 3.3 lbx timing diagrams this section describes the timing relationship be- tween the lbx control signals and the interface buses. 3.3.1 hig [ 4:0 ] command timing the commands driven on hig [ 4:0 ] can cause the host address bus and/or the host data bus to be driven and latched. the following timing diagram il- lustrates the timing relationship between the driven command and the buses. the ``host bus'' in figure 4 could be address and/or data. note that the drive command takes two cycles to drive the host data bus, but only one to drive the address. when the nopc command is sampled, the lbx takes only one cycle to release the host bus. the drive commands in figure 4 are any of the following: cmr cprf cpra cprb cprq dpra dpwa adcpy dacpyh dacpyl drvff the latch command in figure 4 is any of the following: swb0 swb1 swb2 swb3 pcmwq pcmwfq pcmwnq pcpwl mcp3l mcp2l mcp1l pcpwh mcp3h mcp2h lcprad pscd 290478 5 figure 4. hig [ 4:0 ] command timing 21
82433lx/82433nx 3.3.2 hig [ 4:0 ] memory read timing figure 5 illustrates the timing relationship between the hig [ 4:0 ] , mig [ 2:0 ] , cas [ 7:0 ] y , and mdle sig- nals for dram memory reads. the delays shown in the diagram do not represent the actual ac timings, but are intended only to show how the delay affects the sequencing of the signals. when the cpu is reading from dram, the hig [ 4:0 ] lines are driven with the cmr command that causes the lbx to drive memory data onto the hd bus. until the md bus is valid, the hd bus is driven with invalid data. when cas [ 7:0 ] y assert, the md bus be- comes valid after the dram cas [ 7:0 ] y access time. the md and mp lines are directed through a synchronous register inside the lbx to the hd and hp lines. mdle acts as a clock enable for this regis- ter. when mdle is asserted, the lbx samples the md and mp lines. when mdle is negated, the md and hd register retains its current value. the lbx releases the hd bus based on sampling the nopc command on the hig [ 4:0 ] lines and mdle being asserted. by delaying the release of the hd bus until mdle is asserted, the lbx provides hold time for the data with respect to the write en- able strobes (cwe [ 7:0 ] y ) of the second level cache. 290478 6 figure 5. cpu read from memory 22
82433lx/82433nx 3.3.3 mig [ 2:0 ] command figure 6 illustrates the timing of the mig [ 2:0 ] com- mands with respect to the md bus, cas [ 7:0 ] y , and we y . figure 6 shows the md bus transitioning from a read to a write cycle. the latch command in figure 6 is any of the following: pmrfq pmrnq the retire command in figure 6 is any of the following: rcmwq rpmwq rpmwqs the data on the md bus is sampled at the end of the first cycle into the lbx based on sampling the latch command. the cas [ 7:0 ] y signals can be negated in the next cycle. the we y signal is asserted in the next cycle. the required delay between the asser- tion of we y and the assertion of cas [ 7:0 ] y means that the md bus has 2 cycles to turn around; hence the nopm command driven in the second clock. the lbx starts to drive the md bus based on sam- pling the retire command at the end of the third clock. after the retire command is driven for 1 cy- cle, the data is held at the output by the memdrv command. the lbx releases the md bus based on sampling the nopm command at the end of the sixth clock. 290478 7 figure 6. mig [ 2:0 ] command timing 23
82433lx/82433nx 3.3.4 pig [ 3:0 ] command, drvpci, and ppout timing figure 7 illustrates the timing of the pig [ 3:0 ] com- mands, the drvpci signal, and the ppout [ 1:0 ] sig- nal relative to the pci ad [ 31:0 ] lines. the drive commands in figure 7 are any of the fol- lowing: spmrh spmrl spmrn dcpwa dcpwd dcpwl scpa the latch commands in figure 7 are any of the fol- lowing: ppmwa ppmwd lpma the following commands do not fit in either catego- ry, although they function like latch type commands with respect to the ppout [ 1:0 ] signals. they are described in section 3.3.5. lcprf lcpra lcprb the drvpci signal is driven synchronous to the pci bus, enabling the lbxs to initiate driving the pci ad [ 31:0 ] lines one clock after drvpci is asserted. as shown in figure 7, if drvpci is asserted in cycle n, the pci ad [ 31:0 ] lines are driven in cycle n a 1. the negation of the drvpci signal causes the lbxs to asynchronously release the pci bus, enabling the lbxs to cease driving the pci ad [ 31:0 ] lines in the same clock that drvpci is negated. as shown in figure 7, if drvpci is negated in cycle n, the pci ad [ 31:0 ] lines are released in cycle n. pci address and data parity is available at the lbx interface on the ppout lines from the lbx. the par- ity for data flow from pci to lbx is valid 1 clock cycle after data on the ad bus. the parity for data flow from lbx to pci is valid in the same cycle as the data. when the ad [ 31:0 ] lines transition from input to output, there is no conflict on the parity lines due to the dead cycle for bus turnaround. this is illustrated in the sixth and seventh clock of figure 7. 290478 8 figure 7. pig [ 3:0 ] command timing 24
82433lx/82433nx 3.3.5 pig [ 3:0 ] : read prefetch buffer command timing the structure of the cpu-to-pci read prefetch buffer requires special considerations due to the partition of the pcmc and lbx. the pcmc interfaces only to the pci control signals, while the lbxs interface only to the data. therefore, it is not possible to latch a dword of data into the prefetch buffer after it is quali- fied by trdy y . instead, the data is repetitively latched into the same location until trdy y is sam- pled asserted. only after trdy y is sampled assert- ed is data valid in the buffer. a toggling mechanism is implemented to advance the write pointer to the next dword after the current dword has been quali- fied by trdy y . other considerations of the partition are taken into account on the host side as well. when reading from the buffer, the command to drive the data onto the host bus is sent before it is known that the entry is valid. this method avoids the wait-state that would be introduced by waiting for an entry's trdy y to be asserted before sending the command to drive the entry onto the host bus. the fifo structure of the buffer also necessitates a toggling scheme to ad- vance to the next buffer entry after the current entry has been successfully driven. also, this method gives the lbx the ability to drive the same dword twice, enabling reads of less than a dword to be serviced by the buffer; reads of individual bytes of a dword would read the same dword 4 times. the hig [ 4:0 ] and pig [ 3:0 ] lines are defined to en- able the features described previously. the lcprf pig [ 3:0 ] command latches the first pci read dword into the first location in the cpu-to-pci read prefetch buffer. this command is driven until trdy y is sam- pled asserted. the valid dword would then be in the first location of the buffer. the cycle after trdy y is sampled asserted, the pcmc drives the lcpra command on the pig [ 3:0 ] lines. this action latches the value on the pci ad [ 31:0 ] lines into the next dword location in the buffer. again, the lcpra com- mand is driven until trdy y is sampled asserted. each cycle the lcpra command is driven, data is latched into the same location in the buffer. when trdy y is sampled asserted, the pcmc drives the lcprb command on the pig [ 3:0 ] lines. this latches the value on the ad [ 31:0 ] lines into the next location in the buffer, the one after the location that the previ- ous lcpra command latched data into. after trdy y has been sampled asserted again, the com- mand switches back to lcpra. in this way, the same location in the buffer can be filled repeatedly until valid, and when it is known that the location is valid, the next location can be filled. the commands for the hig [ 4:0 ] , cprf, cpra, and cprb, work exactly the same way. if the same com- mand is driven, the same data is driven. driving an appropriately different command results in the next data being driven. figure 8 illustrates the usage of these commands. 25
82433lx/82433nx 290478 9 figure 8. pig [ 3:0 ] cpu-to-pci read prefetch buffer commands figure 8 shows an example of how the pig com- mands function on the pci side. the lcprf com- mand is driven on the pig [ 3:0 ] lines until trdy y is sampled asserted at the end of the fifth pci clock. the lcpra command is then driven until trdy y is again sampled asserted at the end of the seventh pci clock. trdy y is sampled asserted again so lcprb is driven only once. finally, lcpra is driven again until the last trdy y is asserted at the end of the tenth pci clock. in this way, 4 dwords are latched in the read cpu-to-pci prefetch buffer. figure 8 also shows an example of how the hig commands function on the host side of the lbx. two clocks after sampling the cprf command, the lbx drives the host data bus. the data takes two cycles to become stable. the first data driven in this case is invalid, since the data has not arrived on pci. the data driven on the host bus changes in the sev- enth host clock, since the lcprf command has been driven on the pig [ 3:0 ] lines the previous cycle, latching a new value into the first location of the read prefetch buffer. at this point the data is not the cor- rect value, since trdy y has not yet been asserted on pci. the lcprf command is driven again in the fifth pci clock while trdy y is sampled asserted at the end of this clock. the requested data for the read is then latched into the first location of the read prefetch buffer and driven onto the host data bus, becoming valid at the end of cpu clock 12. the brdy y signal can therefore be driven asserted in this clock. the following read transaction (issued in cpu clock 15) requests the next dword, and so the cpra command is driven on the hig [ 4:0 ] lines, ad- vancing to read the next location in the read pre- fetch buffer. as the correct data is already there, the command is driven only once for this transaction. the next read transaction requests data in the same dword as the previous. therefore, the cpra com- mand is driven again, the buffer is not advanced, and the same dword is driven onto the host bus. 26
82433lx/82433nx 3.3.6 pig [ 3:0 ] : end-of-line warning signals: eol when posting pci master writes, the pcmc must be informed when the line boundary is about to be over- run, as it has no way of determining this itself (recall that the pcmc does not receive any address bits from pci). the low order lbx determines this, as it contains the low order bits of the pci master write address and also tracks how many dwords of write data have been posted. therefore, the low order lbx component sends the ``end-of-line'' warning to the pcmc. this is accomplished with the eol signal driven from the low order lbx to the pcmc. figure 9 illustrates the timing of this signal. 1. the frame y signal is sampled asserted in the first cycle. the lpma command is driven on the pig [ 3:0 ] signals to hold the address while it is being decoded (e.g. in the memcs y decode cir- cuit of the 82378 sio). the first data (d0) remains on the bus until trdy y is asserted in response to memcs y being sampled asserted in the third clock. 2. the ppmwa command is driven in response to sampling memcs y asserted. trdy y is asserted in this cycle indicating that d0 has been latched at the end of the fourth clock. the action of the ppmwa command is to transfer the pci address captured in the pci ad latch at the end of the first clock to the posting buffer, and open the pci ad latch in order to capture the data. this data will be posted to the write buffer in the following cycle by the ppmwd command. 3. the eol signal is first negated when the lpma command is driven on the pig [ 3:0 ] signals. how- ever, if the first data dword accepted is also the last that should be accepted, the eol signal will be asserted in the third clock. this is the ``end-of- line'' indication. in this case, the eol signal is as- serted as soon as the lpma command has been latched. the action by the pcmc in response is to negate trdy y and assert stop y in the fifth clock. note that the eol signal is asserted even before the memcs y signal is sampled asserted in this case. the eol signal will remain asserted until the next time the lpma command is driven. 4. if the second dword is the last that should be accepted, the eol signal will be asserted in the fifth clock to negate trdy y and assert stop y on the following clock. the eol signal is asserted in response to the ppmwa command being sam- pled, and relies on the knowledge that trdy y for the first dword of data will be sampled asserted by the master in the same cycle (at the end of the fourth clock). therefore, to prevent a third asser- tion of trdy y in the sixth clock, the eol signal must be asserted in the fifth clock. 290478 10 figure 9. eol signal timing for pci master writes 27
82433lx/82433nx a similar sequence is defined for pci master reads. while it is possible to know when to stop driving read data due to the fact that the read address is latched into the pcmc before any read data is driven on pci, the use of the eol signal for pci master reads sim- plifies the logic internal to the pcmc. figure 10 illus- trates the timing of eol with respect to the pig [ 3:0 ] commands to drive out pci read data. note that unlike the pci master write sequence, the stop y signal is asserted with the last data transfer, not after. 1. the lpma command sampled at the end of the second clock causes the eol signal to assert if there is only one dword left in the line, otherwise it will be negated. the first trdy y will also be the last, and the stop y signal will be asserted with trdy y . 2. the spmrh command causes the count of the number of dwords left in the line to be decre- mented. if this count reaches one, the eol signal is asserted. the next trdy y will be the last, and stop y is asserted with trdy y . 290478 11 figure 10. eol signal timing for pci master reads 28
82433lx/82433nx 3.4 pll loop filter components as shown in figure 11, loop filter components are required on the lbx components. a 4.7 k x 5% re- sistor is typically connected between pins lp1 and lp2. pin lp2 has a path to the pllagnd pin through a 100 x 5% series resistor and a 0.01 m f 10% series capacitor. the ground side of capacitor c1 and the pllvss pin should connect to the ground plane at a common point. all pll loop filter traces should be kept to minimal length and should be wider than signal traces. inductor l1 is connect- ed to the 5v power supply on both the 82433lx and 82433nx. some circuit boards may require filtering the power circuit to the lbx pll. the circuit shown in figure 11 will typically enable the lbx pll to have higher noise immunity than without. pin pllvdd is con- nected to the 5v v cc through a 10 x 5% resistor. the pllvdd and pllvss pins are bypassed with a 0.01 m f 10% series capacitor. the high order 82433nx lbx samples a11 at the falling edge of reset to configure the lbx for pll test mode. when a11 is sampled low, the lbx is in normal operating mode. when a11 is sampled high, the lbx drives the internal hclk from the pll on the eol pin. note that a11 on the high order lbx is connected to the a27 line on the cpu address bus. this same address line is used to put the pcmc into pll test mode. mercury mercury neptune 60 mhz 66 mhz r1 4.7 k x 2.2 k x 4.7 k x r2 100 x 100 x 100 x c2 0.01 m f 0.01 m f 0.01 m f r3 10 x 10 x 10 x c1 0.47 m f 0.47 m f 0.47 m f c1 1 0.01 m f 0.01 m f 0.01 m f 290478 12 figure 11. loop filter circuit 29
82433lx/82433nx 3.5 pci clock considerations there is a 1.25 ns clock skew specification between the pcmc and the lbx that must be adhered to for proper operation of the pcmc/lbx timing. as shown in figure 12, the pcmc drives pclkout to an external clock driver which supplies copies of pclk to pci devices, the lbxs, and back to the pcmc. the skew specification is defined as the dif- ference in timing between the signal that appears at the pcmc pclkin input pin and the signal that ap- pears at the lbx pclk input pin. for both the low order lbx and the high order lbx, the pclk rising and falling edges must not be more than 1.25 ns apart from the rising and falling edge of the pcmc pclkin signal. 290478 13 figure 12. clock considerations 30
82433lx/82433nx 4.0 electrical characteristics 4.1 absolute maximum ratings table 4 lists stress ratings only. functional operation at these maximums is not guaranteed. functional operation conditions are given in sections 4.2 and 4.3. extended exposure to the absolute maximum rat- ings may affect device reliability. case temperature under bias 0 cto a 85 c storage temperature b 40 cto a 125 c voltage on any pin with respect to ground b 0.3 to v cc a 0.3v supply voltage with respect to v ss b 0.3 to a 7.0v maximum power dissipation: 1.4w (82433lx) maximum total power dissipation 1.4w (82433nx) maximum power dissipation, v cc3 430 mw the maximum total power dissipation in the 82433nx on the v cc and v cc3 pins is 1.4w. the v cc3 pins may draw as much as 430 mw, however, total power will not exceed 1.4w. notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 4.2 thermal characteristics the lbx is designed for operation at case temperatures between 0 c and 85 c. the thermal resistances of the package are given in the following tables. table 4. thermal resistance parameter air flow rate (linear feet per minute) 0 400 600 i ja ( c/watt) 51.9 37.1 34.8 i jc ( c/watt) 10 31
82433lx/82433nx 4.3 dc characteristics host interface signals a [ 15:0 ] (t/s), d [ 31:0 ] (t/s), hig [ 4:0 ] (in), hp [ 3:0 ] (t/s) main memory (dram) interface signals md [ 31:0 ] (t/s), mp [ 3:0 ] (t/s), mig [ 2:0 ] (in), mdle(in) pci interface signals ad [ 15:0 ] (t/s), trdy y (in), pig [ 3:0 ] (in), drvpci(in), eol(t/s), ppout(t/s) reset and clock signals hclk(in), pclk(in), reset(in), lp1(out), lp2(in), test(in) 4.3.1 82433lx lbx dc characteristics functional operating range: v cc e 4.75 v to 5.25v; t case e 0 cto a 85 c symbol parameter min typical max unit notes v il1 input low voltage b 0.3 0.8 v 1 v ih1 input high voltage 2.0 v cc a 0.3 v 1 v il2 input low voltage b 0.3 0.3 c v cc v2 v ih2 input high voltage 0.7 c v cc v cc a 0.3 v 2 v ol1 output low voltage 0.4 v 3 v oh1 output high voltage 2.4 v 3 v ol2 output low voltage 0.5 v 4 v oh2 output high voltage v cc b 0.5 v 4 i ol1 output low current 1 ma 5 i oh1 output high current b 1ma5 i ol2 output low current 3 ma 6 i oh2 output high current b 2ma6 32
82433lx/82433nx functional operating range: v cc e 4.75v to 5.25v; t case e 0 cto a 85 c (continued) symbol parameter min typical max unit notes i ol3 output low current 3 ma 7 i oh3 output high current b 1ma7 i ih input leakage current a 10 m a i il input leakage current b 10 m a c in input capacitance 4.6 pf c out output capacitance 4.3 pf c i/o i/o capacitance 4.6 pf notes: 1. v il1 and v ih1 apply to the following signals: ad [ 15:0 ] ,a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] , trdy y , reset, hclk, pclk 2. v il2 and v ih2 apply to the following signals: hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , mdle, drvpci 3. v ol1 and v oh1 apply to the following signals: ad [ 15:0 ] ,a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] 4. v ol2 and v oh2 apply to the following signals: ppout, eol 5. i ol1 and i oh1 apply to the following signals: ppout, eol 6. i ol2 and i oh2 apply to the following signals: ad [ 15:0 ] 7. i ol3 and i oh3 apply to the following signals: a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] 4.3.2 82433nx lbx dc characteristics functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135 to 3.465v, t case e 0 cto a 85 c symbol parameter min typical max unit notes v il1 input low voltage b 0.3 0.8 v 1 v ih1 input high voltage 2.0 v cc a 0.3 v 1 v il2 input low voltage b 0.3 0.3 x v cc v2 v ih2 input high voltage 0.7 x v cc v cc a 0.3 v 2 v il3 input low voltage b 0.3 0.8 v 3 v ih3 input high voltage 2.0 v cc3 a 0.3 v 3 v ol1 output low voltage 0.4 v 4 v oh1 output high voltage 2.4 v 4 v ol2 output low voltage 0.5 v 5 v oh2 output high voltage v cc b 0.5 v 5 i ol1 output low current 1 ma 6 i oh1 output high current b 1ma6 i ol2 output low current 3 ma 7 i oh2 output high current b 2ma7 33
82433lx/82433nx functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c (continued) symbol parameter min typical max unit notes i ol3 output low current 3 ma 8 i oh3 output high current b 1ma8 i ih input leakage current a 10 m a i il input leakage current b 10 m a c in input capacitance 4.6 pf c out output capacitance 4.3 pf c i/o i/o capacitance 4.6 pf notes: 1. v il1 and v ih1 apply to the following signals: ad [ 15:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] , trdy y , reset, hclk, pclk 2. v il2 and v ih2 apply to the following signals: hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , mdle, drvpci 3. v il3 and v ih3 apply to the following signals: a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] 4. v ol1 and v oh1 apply to the following signals: ad [ 15:0 ] ,a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] 5. v ol2 and v oh2 apply to the following signals: ppout, eol 6. i ol1 and i oh1 apply to the following signals: ppout, eol 7. i ol2 and i oh2 apply to the following signals: ad [ 15:0 ] 8. i ol3 and i oh3 apply to the following signals: a [ 15:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] ,md [ 31:0 ] ,mp [ 3:0 ] 9. the output buffers for a [ 15:0 ] ,d [ 31:0 ] and hp [ 3:0 ] are powered with v cc3 and therefore drive 3.3v signal levels. 34
82433lx/82433nx 4.4 82433lx ac characteristics the ac specifications given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, clock high and low times and clock period specifications. figure 13 through figure 21 define these specifications. sections 4.3.1 through 4.3.3 list the ac specifications. in figure 13 through figure 21 vt e 1.5v for the fol- lowing signals: md [ 31:0 ] ,mp [ 3:0 ] ,d [ 31:0 ] , hp [ 3:0 ] ,a [ 15:0 ] ,ad [ 15:0 ] , trdy y , hclk, pclk, reset, test. vt e 2.5v for the following signals: hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , mdle, drvpci, ppout, eol. 4.4.1 host and pci clock timing, 66 mhz (82433lx) functional operating range: v cc e 4.9v to 5.25v; t case e 0 cto a 70 c symbol parameter min max figure notes t1a hclk period 15 20 18 t1b hclk high time 5 18 t1c hclk low time 5 18 t1d hclk rise time 1.5 19 t1e hclk fall time 1.5 19 t1f hclk period stability g 100 ps 1 t2a pclk period 30 18 t2b pclk high time 12 18 t2c pclk low time 12 18 t2d pclk rise time 3 19 t2e pclk fall time 3 19 t3 hclk to pclk skew b 7.2 5.8 21 note: 1. measured on rising edge of adjacent clocks at 1.5 volts. 35
82433lx/82433nx 4.4.2 command timing, 66 mhz (82433lx) functional operating range: v cc e 4.9v to 5.25v; t case e 0 cto a 70 c symbol parameter min max figure notes t10a hig [ 4:0 ] setup time to hclk rising 5.4 15 t10b hig [ 4:0 ] hold time from hclk rising 0 15 t11a mig [ 2:0 ] setup time to hclk rising 5.4 15 t11b mig [ 2:0 ] hold time from hclk rising 0 15 t12a pig [ 3:0 ] setup time to pclk rising 15.6 15 t12b pig [ 3:0 ] hold time from pclk rising b 1.0 15 t13a mdle setup time to hclk rising 5.7 15 t13b mdle hold time to hclk rising b 0.3 15 t14a drvpci setup time to pclk rising 6.5 15 t14b drvpci hold time from pclk rising b 0.5 15 t15a reset setup time to hclk rising 3.1 15 t15b reset hold time from hclk rising 0.3 15 36
82433lx/82433nx 4.4.3 address, data, trdy y , eol, test, tscon and parity timing, 66 mhz (82433lx) functional operating range: v cc e 4.9v to 5.25v; t case e 0 cto a 70 c symbol parameter min max figure notes t20a ad [ 15:0 ] output enable delay from pclk rising 2 17 t20b ad [ 15:0 ] valid delay from pclk rising 2 11 14 1 t20c ad [ 15:0 ] setup time to pclk rising 7 15 t20d ad [ 15:0 ] hold time from pclk rising 0 15 t20e ad [ 15:0 ] float delay from drvpci falling 2 10 16 t21a trdy y setup time to pclk rising 7 15 t21b trdy y hold time from pclk rising 0 15 t22a d [ 31:0 ] ,hp [ 3:0 ] output enable delay from hclk rising 0 7.7 17 2 t22b d [ 31:0 ] ,hp [ 3:0 ] float delay from hclk rising 3.1 15.5 16 t22c d [ 31:0 ] ,hp [ 3:0 ] float delay from mdle rising 2 11.0 16 3 t22d d [ 31:0 ] ,hp [ 3:0 ] valid delay from hclk rising 0 7.7 14 2 t22e d [ 31:0 ] ,hp [ 3:0 ] setup time to hclk rising 3.0 15 t22f d [ 31:0 ] ,hp [ 3:0 ] hold time from hclk rising 0.3 15 t23a ha [ 15:0 ] output enable delay from hclk rising 0 15.2 17 t23b ha [ 15:0 ] float delay from hclk rising 0 15.2 16 t23c ha [ 15:0 ] valid delay from hclk rising 0 16 14 7 t23cc ha [ 15:0 ] valid delay from hclk rising 0 14.5 8 t23d ha [ 15:0 ] setup time to hclk rising 15 15 4 t23e ha [ 15:0 ] setup time to hclk rising 4.1 15 5 t23f ha [ 15:0 ] hold time from hclk rising 0.3 15 t24a md [ 31:0 ] ,mp [ 3:0 ] valid delay from hclk rising 0 12.0 14 6 t24b md [ 31:0 ] ,mp [ 3:0 ] setup time to hclk rising 4.0 15 t24c md [ 31:0 ] ,mp [ 3:0 ] hold time from hclk rising 0.4 15 t25 eol, ppout valid delay from pclk rising 2.3 17.2 14 2 t26a all outputs float delay from tscon falling 0 30 16 t26b all outputs enable delay from tscon rising 0 30 17 notes: 1. min: 0 pf, max: 50 pf 2.0pf 3. when nopc command sampled on previous rising hclk on hig [ 4:0 ] 4. cpu to pci transfers 5. when adcpy command is sampled on hig [ 4:0 ] 6. 50 pf 7. when dacpyl or dacpyh commands are sampled on hig [ 4:0 ] 8. inquire cycle 37
82433lx/82433nx 4.4.4 host and pci clock timing, 60 mhz (82433lx) functional operating range: v cc e 4.75v to 5.25v; t case e 0 cto a 85 c symbol parameter min max figure notes t1a hclk period 16.6 20 18 t1b hclk high time 5.5 18 t1c hclk low time 5.5 18 t1d hclk rise time 1.5 19 t1e hclk fall time 1.5 19 t1f hclk period stability g 100 ps 1 t2a pclk period 33.33 18 t2b pclk high time 13 18 t2c pclk low time 13 18 t2d pclk rise time 3 19 t2e pclk fall time 3 19 t3 pclk to pcmc pclkin: input to input skew b 7.2 5.8 21 notes: 1. measured on rising edge of adjacent clocks at 1.5 volts 4.4.5 command timing, 60 mhz (82433lx) functional operating range: v cc e 4.75v to 5.25v; t case e 0 cto a 85 c symbol parameter min max figure notes t10a hig [ 4:0 ] setup time to hclk rising 6.0 15 t10b hig [ 4:0 ] hold time from hclk rising 0 15 t11a mig [ 2:0 ] setup time to hclk rising 6.0 15 t11b mig [ 2:0 ] hold time from hclk rising 0 15 t12a pig [ 3:0 ] setup time to pclk rising 16.0 15 t12b pig [ 3:0 ] hold time from pclk rising 0 15 t13a mdle setup time to hclk rising 5.9 15 t13b mdle hold time to hclk rising b 0.3 15 t14a drvpci setup time to pclk rising 7.0 15 t14b drvpci hold time from pclk rising b 0.5 15 t15a reset setup time to hclk rising 3.4 15 t15b reset hold time from hclk rising 0.4 15 38
82433lx/82433nx 4.4.6 address, data, trdy y , eol, test, tscon and parity timing, 60 mhz (82433lx) functional operating range: v cc e 4.75v to 5.25v; t case e 0 cto a 85 c symbol parameter min max figure notes t20a ad [ 15:0 ] output enable delay from pclk rising 2 17 t20b ad [ 15:0 ] valid delay from pclk rising 2 11 14 1 t20c ad [ 15:0 ] setup time to pclk rising 7 15 t20d ad [ 15:0 ] hold time from pclk rising 0 15 t20e ad [ 15:0 ] float delay from drvpci falling 2 10 16 t21a trdy y setup time to pclk rising 7 15 t21b trdy y hold time from pclk rising 0 15 t22a d [ 31:0 ] ,hp [ 3:0 ] output enable delay from hclk rising 0 7.9 17 2 t22b d [ 31:0 ] ,hp [ 3:0 ] float delay from hclk rising 3.1 15.5 16 t22c d [ 31:0 ] ,hp [ 3:0 ] float delay from mdle rising 2 11.0 16 3 t22d d [ 31:0 ] ,hp [ 3:0 ] valid delay from hclk rising 0 7.8 14 2 t22e d [ 31:0 ] ,hp [ 3:0 ] setup time to hclk rising 3.4 15 t22f d [ 31:0 ] ,hp [ 3:0 ] hold time from hclk rising 0.3 15 t23a ha [ 15:0 ] output enable delay from hclk rising 0 15.2 17 t23b ha [ 15:0 ] float delay from hclk rising 0 15.2 16 t23c ha [ 15:0 ] valid delay from hclk rising 0 18.5 14 7 t23cc ha [ 15:0 ] valid delay from hclk rising 0 15.5 8 t23d ha [ 15:0 ] setup time to hclk rising 15.0 15 4 t23e ha [ 15:0 ] setup time to hclk rising 4.1 15 5 t23f ha [ 15:0 ] hold time from hclk rising 0.3 15 t24a md [ 31:0 ] ,mp [ 3:0 ] valid delay from hclk rising 0 12.0 14 6 t24b md [ 31:0 ] ,mp [ 3:0 ] setup time to hclk rising 4.4 15 t24c md [ 31:0 ] ,mp [ 3:0 ] hold time from hclk rising 1.0 15 t25 eol, ppout valid delay from pclk rising 2.3 17.2 14 2 t26a all outputs float delay from tscon falling 0 30 16 t26b all outputs enable delay from tscon rising 0 30 17 notes: 1. min: 0 pf, max: 50 pf 2.0pf 3. when nopc command sampled on previous rising hclk on hig [ 4:0 ] 4. cpu to pci transfers 5. when adcpy command is sampled on hig [ 4:0 ] 6. 50 pf 7. when dacpyl or dacpyh commands are sampled on hig [ 4:0 ] 8. inquire cycle 39
82433lx/82433nx 4.4.7 test timing (82433lx) functional operating range: v cc e 4.75v to 5.25v; t case e 0 cto a 85 c symbol parameter min max figure notes t30 all test signals setup time to 10.0 in pll bypass hclk/pclk rising mode t31 all test signals hold time to 12.0 in pll bypass hclk/pclk rising mode t32 test setup time to hclk/pclk rising 15.0 15 t33 test hold time to hclk/pclk rising 5.0 15 t34 ppout valid delay from pclk rising 0.0 500 15 in pll bypass mode 4.5 82433nx ac characteristics the ac specifications given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, clock high and low times and clock period specifications. figure 13 through figure 21 define these specifications. section 4.5 lists the ac specifi- cations. in figure 13 through figure 21 vt e 1.5v for the following signals: md [ 31:0 ] ,mp [ 3:0 ] ,d [ 31:0 ] ,hp [ 3:0 ] , a [ 15:0 ] ,ad [ 15:0 ] , trdy y , hclk, pclk, reset, test. vt e 2.5v for the following signals: hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , mdle, drvpci, ppout, eol. 4.5.1 host and pci clock timing, (82433nx) functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c symbol parameter min max figure notes t1a hclk period 15 20 18 t1b hclk high time 5 18 t1c hclk low time 5 18 t1d hclk rise time 1.5 19 t1e hclk fall time 1.5 19 t1f hclk period stability g 100 ps 1 t2a pclk period 30 18 t2b pclk high time 12 18 t2c pclk low time 12 18 t2d pclk rise time 3 19 t2e pclk fall time 3 19 t3 hclk to pclk skew b 7.2 5.8 21 note: 1. measured on rising edge of adjacent clocks at 1.5 volts. 40
82433lx/82433nx 4.5.2 command timing, (82433nx) functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c symbol parameter min max figure notes t10a hig [ 4:0 ] setup time to hclk rising 5.5 15 t10b hig [ 4:0 ] hold time from hclk rising 0 15 t11a mig [ 2:0 ] setup time to hclk rising 5.5 15 t11b mig [ 2:0 ] hold time from hclk rising 0 15 t12a pig [ 3:0 ] setup time to pclk rising 14.5 15 t12b pig [ 3:0 ] hold time from pclk rising 0.0 15 t13a mdle setup time to hclk rising 5.5 15 t13b mdle hold time to hclk rising b 0.3 15 t14a drvpci setup time to pclk rising 7.0 15 t14b drvpci hold time from pclk rising b 0.5 15 t15a reset setup time to hclk rising 3.4 15 t15b reset hold time from hclk rising 0.4 15 4.5.3 address, data, trdy y , eol, test, tscon and parity timing, (82433nx) functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c symbol parameter min max figure notes t20a ad [ 15:0 ] output enable delay from pclk rising 2 17 t20b ad [ 15:0 ] valid delay from pclk rising 2 11 14 1 t20c ad [ 15:0 ] setup time to pclk rising 7 15 t20d ad [ 15:0 ] hold time from pclk rising 0 15 t20e ad [ 15:0 ] float delay from drvpci falling 2 10 16 t21a trdy y setup time to pclk rising 7 15 t21b trdy y hold time from pclk rising 0 15 t22a d [ 31:0 ] ,hp [ 3:0 ] output enable delay from hclk rising 0 7.5 17 2 t22b d [ 31:0 ] ,hp [ 3:0 ] float delay from hclk rising 3.1 15.5 16 t22c d [ 31:0 ] ,hp [ 3:0 ] float delay from mdle rising 2 9.5 16 3 t22d d [ 31:0 ] ,hp [ 3:0 ] valid delay from hclk rising 0 7.5 14 2 t22e d [ 31:0 ] ,hp [ 3:0 ] setup time to hclk rising 3.1 15 t22f d [ 31:0 ] ,hp [ 3:0 ] hold time from hclk rising 0.3 15 41
82433lx/82433nx functional operating range: v cc e 4.75v to 5v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c (continued) symbol parameter min max figure notes t23a ha [ 15:0 ] output enable delay from hclk rising 0 13.5 17 t23b ha [ 15:0 ] float delay from hclk rising 0 13.5 16 t23c ha [ 15:0 ] valid delay from hclk rising 0 17.5 14 7 t23cc ha [ 15:0 ] valid delay from hclk rising 0 13.5 8 t23d ha [ 15:0 ] setup time to hclk rising 15 15 4 t23e ha [ 15:0 ] setup time to hclk rising 4.2 15 5 t23f ha [ 15:0 ] hold time from hclk rising 0.3 15 t24a md [ 31:0 ] ,mp [ 3:0 ] valid delay from hclk rising 0 12.0 14 6 t24b md [ 31:0 ] ,mp [ 3:0 ] setup time to hclk rising 4.4 15 t24c md [ 31:0 ] ,mp [ 3:0 ] hold time from hclk rising 1.0 15 t25 eol, ppout valid delay from pclk rising 2.3 17.2 14 2 t26a all outputs float delay from tscon falling 0 30 16 t26b all outputs enable delay from tscon rising 0 30 17 note: 1. min: 0 pf, max: 50 pf 2.0pf 3. when nopc command sampled on previous rising hclk on hig [ 4:0 ] 4. cpu to pci transfers 5. when adcpy command is sampled on hig [ 4:0 ] 6. 50 pf 7. when dacpyl or dacpyh commands are sampled on hig [ 4:0 ] 8. inquire cycle 4.5.4 test timing (82433nx) functional operating range: v cc e 4.75v to 5.25v; v cc3 e 3.135v to 3.465v, t case e 0 cto a 85 c symbol parameter min max figure notes t30 all test signals setup time to hclk/ 10.0 in pll bypass mode pclk rising t31 all test signals hold time to hclk/ 12.0 in pll bypass mode pclk rising t32 test setup time to hclk/pclk rising 15.0 15 t33 test hold time to hclk/pclk rising 5.0 15 t34 ppout valid delay from pclk rising 0.0 500 15 in pll bypass mode 42
82433lx/82433nx 4.5.5 timing diagrams 290478 14 figure 13. propagation delay 290478 15 figure 14. valid delay from rising clock edge 290478 16 figure 15. setup and hold times 290478 17 figure 16. float delay 290478 18 figure 17. output enable delay 43
82433lx/82433nx 290478 19 figure 18. clock high and low times and period 290478 20 figure 19. clock rise and fall times 290478 21 figure 20. pulse width 290478 22 figure 21. output to output delay 44
82433lx/82433nx 5.0 pinout and package information 5.1 pin assignment pins 1, 22, 41, 61, and 150 are vdd3 pins on the 82433nx. these pins must be connected to the 3.3v power supply. all other vdd pins on the 82433nx must be connected to the 5v power supply. 290478 23 figure 22. 82433lx and 82433nx pin assignment 45
82433lx/82433nx table 5. 82433lx and 82433nx numerical pin assignment pin name pin y type v dd (82433lx) 1 v v dd3 (82433nx) v ss 2v pllv dd 3v pllv ss 4v pllagnd 5 v lp2 6 in lp1 7 out hclk 8 in test 9 in d6 10 t/s d2 11 t/s d14 12 t/s d12 13 t/s d11 14 t/s hp1 15 t/s d4 16 t/s d0 17 t/s d16 18 t/s tscon 19 in v ss 20 v v ss 21 v v dd (82433lx 22 v v dd 3 (82433nx) d20 23 t/s d18 24 t/s hp3 25 t/s pin name pin y type d22 26 t/s hp2 27 t/s d25 28 t/s d17 29 t/s d19 30 t/s d23 31 t/s a14 32 t/s a12 33 t/s a8 34 t/s a6 35 t/s a10 36 t/s a3 37 t/s a4 38 t/s a9 39 t/s v dd 40 v v dd (82433lx) 41 v v dd 3 (82433nx) v ss 42 v a2 43 t/s a1 44 t/s a0 45 t/s a5 46 t/s a15 47 t/s a13 48 t/s a11 49 t/s a7 50 t/s pin name pin y type d21 51 t/s d24 52 t/s d27 53 t/s d31 54 t/s d30 55 t/s d26 56 t/s d29 57 t/s d28 58 t/s v ss 59 v v ss 60 v v dd (82433lx) 61 v v dd3 (82433nx) hig0 62 in hig1 63 in hig2 64 in hig3 65 in hig4 66 in mig0 67 in mig1 68 in mig2 69 in md8 70 t/s md24 71 t/s md0 72 t/s md16 73 t/s md9 74 t/s md25 75 t/s 46
82433lx/82433nx table 5. 82433lx and 82433nx numerical pin assignment (continued) pin name pin y type md1 76 t/s md17 77 t/s md10 78 t/s v ss 79 v v dd 80 v v dd 81 v trdy y 82 in reset 83 in md26 84 t/s md2 85 t/s md18 86 t/s md11 87 t/s md27 88 t/s md3 89 t/s md19 90 t/s md12 91 t/s md28 92 t/s md4 93 t/s v dd 94 v md20 95 t/s v ss 96 v v ss 97 v md13 98 t/s md29 99 t/s md5 100 t/s md21 101 t/s md14 102 t/s md30 103 t/s md6 104 t/s pin name pin y type md22 105 t/s md15 106 t/s md31 107 t/s md7 108 t/s md23 109 t/s v dd 110 v v ss 111 v mp0 112 t/s mp2 113 t/s mp1 114 t/s mp3 115 t/s ad0 116 t/s ad1 117 t/s ad2 118 t/s ad3 119 t/s v dd 120 v v dd 121 v ppout 122 t/s eol 123 t/s v ss 124 v ad4 125 t/s ad5 126 t/s ad6 127 t/s ad7 128 t/s ad8 129 t/s v dd 130 v ad9 131 t/s ad10 132 t/s pin name pin y type ad11 133 t/s ad12 134 t/s ad13 135 t/s ad14 136 t/s ad15 137 t/s mdle 138 in v dd 139 v v ss 140 v v ss 141 v pclk 142 in drvpci 143 in pig3 144 in pig2 145 in pig1 146 in pig0 147 in d7 148 t/s v ss 149 v v dd (82433lx) 150 v v dd 3 (82433nx) hp0 151 t/s d8 152 t/s d1 153 t/s d5 154 t/s d3 155 t/s d10 156 t/s d15 157 t/s d13 158 t/s d9 159 t/s v dd 160 v 47
82433lx/82433nx table 6. 82433lx and 82433nx alphabetical pin assignment list pin name pin y type a0 45 t/s a1 44 t/s a2 43 t/s a3 37 t/s a4 38 t/s a5 46 t/s a6 35 t/s a7 50 t/s a8 34 t/s a9 39 t/s a10 36 t/s a11 49 t/s a12 33 t/s a13 48 t/s a14 32 t/s a15 47 t/s ad0 116 t/s ad1 117 t/s ad2 118 t/s ad3 119 t/s ad4 125 t/s ad5 126 t/s ad6 127 t/s ad7 128 t/s ad8 129 t/s ad9 131 t/s ad10 132 t/s ad11 133 t/s ad12 134 t/s pin name pin y type ad13 135 t/s ad14 136 t/s ad15 137 t/s d0 17 t/s d1 153 t/s d2 11 t/s d3 155 t/s d4 16 t/s d5 154 t/s d6 10 t/s d7 148 t/s d8 152 t/s d9 159 t/s d10 156 t/s d11 14 t/s d12 13 t/s d13 158 t/s d14 12 t/s d15 157 t/s d16 18 t/s d17 29 t/s d18 24 t/s d19 30 t/s d20 23 t/s d21 51 t/s d22 26 t/s d23 31 t/s d24 52 t/s d25 28 t/s pin name pin y type d26 56 t/s d27 53 t/s d28 58 t/s d29 57 t/s d30 55 t/s d31 54 t/s drvpci 143 in eol 123 t/s hclk 8 in hig0 62 in hig1 63 in hig2 64 in hig3 65 in hig4 66 in hp0 151 t/s hp1 15 t/s hp2 27 t/s hp3 25 t/s lp1 7 out lp2 6 in md0 72 t/s md1 76 t/s md2 85 t/s md3 89 t/s md4 93 t/s md5 100 t/s md6 104 t/s md7 108 t/s md8 70 t/s 48
82433lx/82433nx table 6. 82433lx and 82433nx alphabetical pin assignment list (continued) pin name pin y type md9 74 t/s md10 78 t/s md11 87 t/s md12 91 t/s md13 98 t/s md14 102 t/s md15 106 t/s md16 73 t/s md17 77 t/s md18 86 t/s md19 90 t/s md20 95 t/s md21 101 t/s md22 105 t/s md23 109 t/s md24 71 t/s md25 75 t/s md26 84 t/s md27 88 t/s md28 92 t/s md29 99 t/s md30 103 t/s md31 107 t/s mdle 138 in mig0 67 in pin name pin y type mig1 68 in mig2 69 in mp0 112 t/s mp1 114 t/s mp2 113 t/s mp3 115 t/s pclk 142 in pig0 147 in pig1 146 in pig2 145 in pig3 144 in pllagnd 5 v pllv dd 3v pllv ss 4v ppout 122 t/s reset 83 in test 9 in trdy 82 in tscon 19 in v dd (82433lx) 1 v v dd 3 (82433nx) v dd (82433lx) 22 v v dd 3 (82433nx) v dd 40 v v dd (82433lx) 41 v v dd 3 (82433nx) v dd (82433lx) 61 v v dd 3 (82433nx) pin name pin y type v dd 80 v v dd 81 v v dd 94 v v dd 110 v v dd 120 v v dd 121 v v dd 130 v v dd 139 v v dd (82433lx) 150 v v dd 3 (82433nx) v dd 160 v v ss 2v v ss 20 v v ss 21 v v ss 42 v v ss 59 v v ss 60 v v ss 79 v v ss 96 v v ss 97 v v ss 111 v v ss 124 v v ss 140 v v ss 141 v v ss 149 v 49
82433lx/82433nx 5.2 package information 290478 24 figure 23. 82433lx and 82433nx 160-pin qfp package table 7. 160-pin qfp package values symbol min value max value (mm) (mm) a 4.45 a1 0.25 0.65 a2 3.30 3.80 b 0.20 0.40 d 31.00 32.40 d1 27.80 28.20 d3 25.55 symbol min value max value (mm) (mm) e 31.60 32.40 e1 27.80 28.20 e3 25.55 e 0.65 l 0.60 1.00 i 0 10 g 0.1 50
82433lx/82433nx 6.0 testability the tscon pin may be used to help test circuits surrounding the lbx. during normal operations, the tscon pin must be tied to vcc or connected to vcc through a pull-up resistor. all lbx outputs are tri-stated when the tscon pin is held low or grounded. 6.1 nand tree a nand tree is provided in the lbx for automated test equipment (ate) board level testing. the nand tree allows the tester to set the connectivity of each of the lbx signal pins. the following steps must be taken to put the lbx into pll bypass mode and enable the nand tree. first, to enable pll bypass mode, drive reset in- active, test active, and the dcpwa command (0100) on the pig [ 3:0 ] lines. then drive pclk from low to high. drvpci must be held low on all rising edges of pclk during testing in order to ensure that the lbx does not drive the ad [ 15:0 ] lines. the host and memory buses are tri-stated by driving nopm (000) and nopc (00000) on the mig [ 2:0 ] and hig [ 4:0 ] lines and driving two rising edges on hclk. a rising edge on pclk with reset high will cause the lbxs to exit pll bypass mode. test must remain high throughout the use of the nand tree. the combination of test and drvpci high with a rising edge of pclk must be avoided. tscon must be driven high throughout testing since driving it low would tri-state the output of the nand tree. a 10 ns hold time is required on all inputs sampled by pclk or hclk when in pll bypass mode. 6.1.1 test vector table the following test vectors can be applied to the 82433lx and 82433nx to put it into pll bypass mode and to enable nand tree testing. 6.1.2 nand tree table table 9 shows the sequence of the nand tree in the 82433lx and 82433nx. non-inverting inputs are driven directly into the input of a nand gate in the tree. inverting inputs are driven into an inverter be- fore going into the nand tree. the output of the nand tree is driven on the ppout pin. table 8. test vectors to put lbx into pll bypass and enable nand tree testing lbx 1234567891011 pin/vector y pclk 0 1 0 0 1 1 1 1 1 1 1 pig [ 3:0 ] 0h 0h 0h 4h 4h 4h 4h 4h 4h 4h 4h reset 1 1 1 0 0 0 1 1 1 1 1 hclk 0 0 0 0 0 0 0 1 0 1 0 mig [ 2:0 ] 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h hig [ 4:0 ] 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h test 1 1 1 1 1 1 1 1 1 1 1 drvpci 0 0 0 0 0 0 0 0 0 0 0 51
82433lx/82433nx table 9. nand tree sequence order pin y signal non- inverting 110d6 y 211d2 y 3 12 d14 y 4 13 d12 y 5 14 d11 y 6 15 hp1 y 716d4 y 817d0 y 9 18 d16 y 10 23 d20 y 11 24 d18 y 12 25 hp3 y 13 26 d22 y 14 27 hp2 y 15 28 d25 y 16 29 d17 y 17 30 d19 y 18 31 d23 y 19 32 a14 y 20 33 a12 y 21 34 a8 y 22 35 a6 y 23 36 a10 y 24 37 a3 y 25 38 a4 y 26 39 a9 y order pin y signal non- inverting 27 43 a2 y 28 44 a1 y 29 45 a0 y 30 46 a5 y 31 47 a15 y 32 48 a13 y 33 49 a11 y 34 50 a7 y 35 51 d21 y 36 52 d24 y 37 53 d27 y 38 54 d31 y 39 55 d30 y 40 56 d26 y 41 57 d29 y 42 58 d28 y 43 62 hig0 y 44 63 hig1 y 45 64 hig2 y 46 65 hig3 y 47 66 hig4 y 48 67 mig0 n 49 68 mig1 n 50 69 mig2 n 51 70 md8 n 52 71 md24 n order pin y signal non- inverting 53 72 md0 n 54 73 md16 n 55 74 md9 n 56 75 md25 n 57 76 md1 n 58 77 md17 n 59 78 md10 n 60 82 trdy y y 61 83 reset n 62 84 md26 n 63 85 md2 n 64 86 md18 n 65 87 md11 n 66 88 md27 n 67 89 md3 n 68 90 md19 n 69 91 md12 n 70 92 md28 n 71 93 md4 n 72 95 md20 n 73 98 md13 n 74 99 md29 n 75 100 md5 n 76 101 md21 n 77 102 md14 n 78 103 md30 n 52
82433lx/82433nx table 9. nand tree sequence (continued) order pin y signal non- inverting 79 104 md6 n 80 105 md22 n 81 106 md15 n 82 107 md31 n 83 108 md7 n 84 109 md23 n 85 112 mp0 n 86 113 mp2 n 87 114 mp1 n 88 115 mp3 n 89 116 ad0 y 90 117 ad1 y 91 118 ad2 y 82 119 ad3 y 93 123 eol y order pin y signal non- inverting 94 125 ad4 y 95 126 ad5 y 96 127 ad6 y 97 128 ad7 y 98 129 ad8 y 99 131 ad9 y 100 132 ad10 y 101 133 ad11 y 102 134 ad12 y 103 135 ad13 y 104 136 ad14 y 105 137 ad15 y 106 138 mdle y 107 143 drvpci n order pin y signal non- inverting 108 144 pig3 n 109 145 pig2 n 110 146 pig1 n 111 147 pig0 n 112 148 d7 y 113 151 hp0 y 114 152 d8 y 115 153 d1 y 116 154 d5 y 117 155 d3 y 118 156 d10 y 119 157 d15 y 120 158 d13 y 121 159 d9 y 6.2 pll test mode the high order 82433nx lbx samples a11 at the falling edge of reset to configure the lbx for pll test mode. when a11 is sampled low, the lbx is in normal operating mode. when a11 is sampled high, the lbx drives the internal hclk from the pll on the eol pin. 53

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